Parallel and Pipeline Processing for Output-Buffer Management in Photonic Packet Switches

Hiroaki Harai and Masayuki Murata y Communications Research Laboratory, Tokyo, Japan z Osaka University, Osaka, Japan Abstract We investigate the mechanism of high-speed buffer management for output-buffered photonic packet switches. We propose a buffer management mechanism on parallel and pipeline processing architecture consisting of log N pipeline stages, whereN is the number of ports of the packet switch. This is an expansion of a simple round-robin scheduling for determining the delays of arriving packets. The pipeline stages consist of a prefix operation part and a delay determination part. The prefix operation part determines the relative delays of arriving packets, assuming that no packet is currently buffered and that all the arriving packets will be buffered based on round-robin scheduling. We achieve speedup by a parallel-prefix operation in this part. The delay determination part gives the delays of packets on all theN ports simultaneously, by using the current status of buffer occupancy and the relative delays. Since the time complexity of each processor in the pipeline stages isO , the throughput of the buffer management isN times larger than that of the round-robin scheduling method. We apply the processing and the architecture to buffer management for asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 128 photonic packet switches with 40Gbps ports, which provide at least ten times as much throughput as the latest electronic IP routers. The proposed mechanism for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show that the degradation in the performance of the mechanism resulting from this overestimation is quite acceptable through simulation experiments.